1. Field of the Invention
The invention relates to an insulating layer/barrier for deposition on a silicon substrate and/or epitaxial silicon surface, composites and structures comprising said insulating layer/barrier, method of making the composites and structure, as well as use of the insulating layer/barrier, composites and structures in the construction of improved semiconductor devices, including but not limited to quantum well, tunneling, metal oxide, SOI, superlattice, and three dimensional architecture. The insulating layer/barrier is formed by combining silicon with one or more elements to form an insulating compound of silicon where one of the possible elements is oxygen, forming a layer of SiOx where 0 less than x less than 2.0. The insulating layer structure is produced in such a way to allow for low defect epitaxial silicon to be deposited next to the insulating layer. It further relates to forming a number of such layers sandwiched between epitaxial silicon.
2. Description of Related Art
1. L. Esaki and R. Tsu, IBM J. Res. and Dev. 14, 61 (1970).
2. R. Tsu and L. Esaki, Appl. Phys. Lett. 22, 562(1973); L L Chang, L. Esaki and R. Tsu, ibid 24 593 (1974).
3. R. Tsu, Nature, 364 19 (1993).
4. R. Tsu, A. Filios, C. Lofgren, D. Cahill, J. Vannostrand and C. G. Wang, Solid-State Electronics Vol. 40, Nos. 1-8, pp. 221-223, 1996.
5. R. Tsu, A. Filios, C. Lofgren, J. Ding, Q. Zhang, J. Morais and C. G. Wang, Proc. 4th Int. Symp. xe2x80x9cQuantum Confinement: Nanoscale Materials, Devices, and Systemsxe2x80x9d, Edited by M. Cahay, J. P. Leburton, D. J. Lockwood, and S. Bandyopadhyay, (ECS proc. Vol. 97-11, 1997) p. 341.
6. J. Ding and R. Tsu, Appl. Phys. Lett., 71, 2124 (1997).
7. J. Morais, R. Lender, and R. Tsu, tobe published, also in Ph.D. Thesis, Unicamp, Brazil, 1996.
8. Inst. Of Semiconductor Physics, Kiev, Ukraine: Preliminary in Litovcheko et al., JVST, B15, 439 (1997).
9. G. I. Distler, and B. B. Zvyagin, Nature, 212, 807-809, (1996).
10. C. A. O. Henning, Nature, 227, 1129-1131 (1970).
11. O. W. Holland, D. Fathy, and D. K. Sadana, Appl. Phys. Lett., 69, 674 (1996).
12. P. P. van der Ziel et al., IEEE Q.E. 22, 1587 (1982).
13. J. W. Matthews and E. E. Blakeslee, J. Crystal. Growth, 32 265 (1976).
14. G. C. Osborn, J. Appl. Phys. 53, 1586 (1982).
15. E. H. Poindexter and P. J. Caplan, in xe2x80x9cIns. Films on Semi,xe2x80x9d Edited by M. Schulz and M. Pensl, (Springer, Berlin 1981) p. 150.
16. E. H. Nicollian and R. Tsu, U.S. Pat. No. 5,051,786, Sep. 24, 1991; R. Tsu, E. H. Nicollian, and A. Reisman, Appl. Phys. Lett. 55, 1897(1989).
17. Q. Y. Ye, R. Tsu and E. H. Nicollian, Phys. Rev. B., 44, 1806 (1991).
18. R. People, IEEE Q.E. 22, 1696(1986).
19. D. G. Deepe et al., Appl. Phys. Lett. 51, 637 (1987).
20. R. Tsu, U.S. Pat. No. 5,216,262 dated Jun. 1, 1993.
21. Nakashima et al, Proc. IEEE, 1994 Int. SOI Conf, 1994.
22. R. Tsu, A. Filios, C. Lofgren, K. Dovidenko, and C. G. Wang, Electrochemical and Solid-State Lett. I (2) 80-82 (1998).
For a general review of quantum devices see:
23. F. Capasso et al. IEEE, Transaction on Electron Devices 36, 2065 (1989).
24. F. Sols et al., Appl. Phys. Lett. 54 350(1989).
25. Kwok Ng, Complete Guide to Semiconductor Devices, McGraw Hill, 1995.
26. S. M. Sze, VLSI Technology, McGraw-Hill, 1983.
the disclosure of each being incorporated herein by reference.
Silicon dioxide (SiO2) has been used for many years as an insulating material in semiconductors. It has excellent insulating properties and provides a potential barrier typically of 3.2 eV. However, when SiO2 is grown adjacent to silicon, there is a high mismatch between monocrystalline or epitaxial silicon and the layer of SiO2 resulting in accumulated stress. These stresses, and therefore strains, cause the SiO2 to become amorphous preventing the subsequent growth of epitaxial layers. Monocrystalline silicon in the semiconductor industry is available in the form of thin round disks called wafers. These single crystal wafers are produced by growing single crystal ingots from molten silicon which are then sliced and polished into a final xe2x80x9cwaferxe2x80x9d upon which semiconductor devices and integrated circuits are manufactured. Matthews and Blakeslee (13) showed that if the thickness of the xe2x80x9cstrainxe2x80x9d layer is thin enough so that the stored strain energy is kept below a critical value, a defect-free superlattice is possible for lattice mismatched systems and hence epitaxial silicon can proceed.
In Tsu U.S. Pat. No. 5,216,262, (20), the disclosure of which is incorporated herein by reference, making alternating thin layers of SiO2 and epitaxial silicon was claimed as a way to make a barrier material adjacent to which epitaxial silicon can be grown with a low number of defects. Although such a barrier is feasible (3,4,22), the cost of controlling the process to precisely deposit SiO2 in thin layers adjacent to epitaxial silicon in a superlattice is difficult and expensive.
Silicon on Insulator (SOI):
Current silicon devices are limited by inherent parasitic circuit elements due primarily to junction capacitance and leakage currents. These problems can be addressed for silicon by fabricating silicon devices in a thin epitaxial layer on top of a buried insulator layer, the so-called silicon on insulator (SOI) approach. This approach allows devices to be isolated from the substrate as well as from each other, eliminating the need for structures such as guard-rings, isolation junctions, etc. (26) 
A number of technologies have been developed to place an insulating layer under a layer of low defect silicon which forms the substrate upon which silicon devices are fabricated. This insulating layer reduces the amount of leakage current as well as the junction capacitance thus significantly improving the device performance. Advantages include substantially reduced power consumption, more efficient low-voltage operation, significantly improved speed, radiation hardening and reduced integrated circuit manufacturing costs. These characteristics make SOI wafers well-suited for many commercial applications, including cellular phones, wireless communications devices, satellites, portable and desktop computers, automotive electronics, and microwave systems.
One method of producing SOI wafers is by implanting oxygen ions below the surface of a silicon wafer in sufficient quantity to transform, with proper annealing, a layer of the silicon to silicon dioxide, while maintaining a thin layer of device quality epitaxial silicon at the surface. During implantation of the oxygen ions through the silicon surface, the surface is damaged reducing the quality of the epi-layer upon which devices are fabricated. Annealing can reduce the oxygen inclusion, however it is difficult to reduce the [0] to values below 1017/cm3. The thickness of the insulating layer is very difficult to control due to the random nature of scattering arising from ion implantation. Also, the ion implantation equipment costs are expensive.
A second method of production is silicon-on-sapphire (xe2x80x9cSOSxe2x80x9d). In SOS technology, circuitry is constructed in a layer of silicon, which has been deposited on a sapphire substrate. This material has been used in the construction of radiation resistant circuits. However, there are several problems with this material, including large current conduction in the sapphire when exposed to radiation, brittleness causing breakage during integrated circuit fabrication and large mismatches between sapphire and silicon crystal structures. These problems have led to performance and manufacturability limitations.
A third method of production involves the bonding of two thin film wafers. In this approach, two bulk silicon wafers, each with a thermally grown oxide layer, are first bonded together to form a silicon/silicon dioxide/silicon wafer. Thin-film bonded wafers are constructed by bonding the two wafers and then thinning one of the two layers. Several alternatives are currently being explored across the industry to perform the subsequent thinning processxe2x80x94including mechanical polishing, chemical etching; plasma assisted chemical etching, bond and selective etching of porous silicon or an implant-enhanced slicing of the wafer. The bonded wafer approach has the advantage that the buried oxide can be made very uniform and thick. The top silicon layer retains its high quality, achieving uniformity in the thickness of the top silicon layer, however, has proven difficult. Also, the requirement to use two silicon wafers with complex processing has, to date, resulted in a relatively high cost structure for bonded wafers.
Quantum Wells:
The p-n homojunction currently widely used in silicon devices has some serious limitations. Typical p-n homojunctions involve long range electrostatic interaction of free charges and are not abrupt. The electrostatic fields are continuous over a distance, which is significantly longer than the DeBroglie wavelength of an electron. It is a scattering dominated structure for electrons. On the other hand heterojunctions are abrupt and analogous to a waterfall where the change in potential is confined to a very short distance. Heterojunctions are the basis of the barriers formed in GaAs/AlGaAs, GaInAs/AlInAs and other so-called III/V compounds from columns 3 and 5 of the periodic chart. The barriers of those heterojunctions derive from chemical bonding, and are short ranged. Typically in p-n homojunctions the continuous voltage changes occur over a distance of the order of one micron. With a heterojunction this occurs over a distance on the order of 0.5 nanometers, less than one percent the p-n junction distance. As the size of transistors decrease with time, the heterojunction will be ever more important, particularly for quantum well structures.
Dr. L. Esaki and Dr. R. Tsu, while working jointly at the IBM research center (1,2), envisioned a new type of man made material which could be used to form what they called superlattice barriers and quantum wells to resolve some of the difficulties of the p-n junction. In order to realize these structures in silicon, a xe2x80x9cbarrierxe2x80x9d material is necessary that can be stacked between epitaxial device grade silicon. The present invention describes such a material.
In his patent 5,216,262, (20) R. Tsu proposed a way to build barriers and quantum wells with silicon and SiO2 which will allow the economical implementation of quantum wells. The invention provided a quantum well structure useful for semi-conducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated. Creating SiO2 in such thin layers is commercially expensive and probably not viable. The present patent describes a substitute for SiO2 in this application, which will be referred to as xe2x80x9csaid barrierxe2x80x9d.
Metal Oxide Devices
The silicon MOSFET is probably the single most important structure of electronic device. (26) A layer of amorphous SiO2 is typically sandwiched between a metal contact (the gate) and silicon channel region between the source and drain. The lower the interface defect density between the amorphous SiO2 and epitaxial silicon, the faster is the switching speed and the less power dissipated. Because of the amorphous nature of current SiO2 layers, the region of the layer near the silicon is filled with defects, reducing the switching speed of the device, apart from the more obvious problem of building epitaxially grown structure beyond the oxide barrier. In his patent 5,216,262 (20) R. Tsu addressed this shortcoming by introducing an insulating layer consisting essentially of alternate strain layers of SiO2 and Si forming a superlattice, each of said layers being so thin that no defects are generated as a result of the release of stored strain energy. By reducing the level of defects at this interface between the insulating layer and the channel region of the device the mobility is increased and performance improved. For reasons stated above forming such layers of SiO2 and Si is expensive. Once again, in this application the xe2x80x9csaid barrierxe2x80x9d described in this patent can be substituted for SiO2.
Two Dimensional Semiconductor Devices
Currently silicon-based integrated circuits are limited to construction as two-dimensional devices. Once an oxide layer is deposited in a semiconductor device, there is currently no way to grow epitaxial silicon again on top of the oxide layer. Epitaxial silicon is needed if a second layer of devices is to be constructed on top of the first layer. Growing additional layers could provide significant advantages in improving heat dissipation, simplifying interconnections between devices, and significantly reducing the size of an integrated circuit, depending on the number of layers of devices stacked on top of each other, as well as, the means by which they are interconnected.
Silicon Dioxide as a Dielectric Material
When SiO2 is used as an insulating layer in semiconductor devices there is a capacitance and resistance associated with such a layer. The capacitance is a function of the area of the contact surface, the thickness of the SiO2 layer and the dielectric constant of the SiO2 material. Currently the contact area and distance between contacts can be changed affecting the capacitance and hence the RC time constant associated with the SiO2 insulating layer. However, the SiO2 dielectric constant is fixed by the properties of SiO2 and there is virtually no ability to change that property.
Accordingly, it is an object of the present invention to overcome the drawbacks and disadvantages of the above-described insulating layers and heterojunctions used in silicon based semiconductor devices. The present invention allows control over the dielectric constant, as well as, the thickness of said barrier.
Si/O
The invention provides a method for the formation of a Si/adsorbed-monolayer-of-oxygen (Si/O) as the building block of a barrier to form a repeatable systemxe2x80x94a superlattice. This Si/O building block can be grown on a silicon substrate where silicon layers are grown epitaxially adjacent to each monolayer, or less, of adsorbed oxygen where therein is formed monolayers, or less, of adsorbed oxygen sandwiched between thin epitaxially grown silicon layers. Since all transport properties depend on both the barrier height and barrier width, and since the barrier width is dictated by the Sixe2x80x94Oxe2x80x94Si thickness which cannot be changed, the formation of a superlattice by repeating the basic building block accomplishes the desired thickness of the barrier. A relatively thick barrier is used as an insulating layer for devices such as in the use of SOI, and thin barriers are used for most quantum devices.
Silicon growth beyond a barrier structure consisting of thin layer (typically, 1-2 nm) of silicon sandwiched between adjacent layers of adsorbed oxygen up to 100 Langmuir of exposure is epitaxial and almost free of stacking faults as determined in high resolution TEM, transmission electron microscopy (reference 22). The measured barrier height in the conduction band of a double barrier structure with 1.1 nm silicon layer sandwiched between two adsorbed monolayers of oxygen is 0.5 eV. The maximum barrier height in the conduction band is probably limited by 1.5 eV, half as large as SiO2, which is 3.2 eV. The rationale is that the interface layer consisting of S/O bonds is closer to SiO rather than SiO2. Since the effectiveness of a barrier depends on both the height and the width of the barrier, to increase the width the basic period, Si/adsorbed O, may be repeated to form a superlattice. A superlattice of Si/O up to nine periods shows excellent epitaxial growth of silicon beyond the superlattice structure, indicating that the major objective has already been accomplished.
The formation of the structure consists of the deposition of silicon by either MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition) onto an epitaxial silicon surface with a controlled adsorption of oxygen. The deposition temperature is generally kept below 650xc2x0 C. to limit possible subsequent desorption of the adsorbed oxygen. The exposure to oxygen is at temperatures generally below 500xc2x0 C. to prevent any migration or re-emission of the adsorbed oxygen. Once the superlattice is formed, silicon capping, usually greater than 4 nm in thickness, can prevent any degradation. Specifically, the structure measured here is Si Substrate/ Si(1.1 nm)xe2x80x94O(10L)xe2x80x94Si(1.1 nm)-)(10L) . . . Si(1.1 nm)xe2x80x94O(10L)/epi-Si Such a structure has exhibited the following:
The current through this superlattice has been reduced more than four orders of magnitude.
Epitaxial silicon after the superlattice is virtually free of stacking faults.
These two facts allow the replacement of SOI by this Si/O superlattice for devices with high speed including high efficiency FET""s currently fabricated on SOI.
A definitive theoretical reason for the formation of epitaxy on apparently disordered adsorbed monolayer of oxygen on silicon is still lacking. It may be due to lateral growth through the xe2x80x9cholesxe2x80x9d in the coverage of the adsorbed oxygen. It may be due to partial screening of the silicon atomic potential by a monolayer of oxygen. More likely, it may be caused by both mechanisms. We now know a third mechanism: The oxygen monolayer at the interface of two silicon surfaces, Sixe2x80x94Oxe2x80x94Si, forms an essentially lattice matched system possibly with a slight twist, resulting in a rotational strain, Subsequent silicon deposition serves to defme this strain region.
EpiSiOx 
The invention also provides a method of introducing oxygen simultaneously during silicon deposition onto a silicon substrate to form a single insulating/barrier layer of silicon and oxygen referred to as EpiSiOx wherein 0 less than x less than 2.0. This structure forms an epitaxial system on silicon in which epitaxial silicon, almost free of defects such as stacking faults and dislocations, can be grown beyond this EpiSiOx. This system is therefore an ideal replacement of SOI presently available. As before, a relatively thick barrier is used as an insulating layer for devices as is done in SOI, and thin barriers are used for most quantum devices.
A layer of EpiSiOx has been formed with the following steps:
All depositions are below 650xc2x0 C.
Oxygen is introduced during the silicon deposition.
A summary of what has been achieved:
The silicon growth beyond the EpiSiOx of thickness below 10 nm may be epitaxial with low defect densities below 109/cm2.
The thinner is the EpiSiOx; the thinner is the silicon deposition beyond the structure for complete recovery. An example to make the point is for a 2 nm EpiSiOx, only 4 nm of silicon is needed to recover the surface reconstruction. Conversely, the thicker is the EpiSiOx, the thicker is the silicon deposition necessary to recover a perfect silicon surface reconstructionxe2x80x94the appearance of surface reconstruction is used as a figure of merit for the recovery of epitaxy.
The following is believed to be a possible basis for the EpiSiOx. The structure is all along epitaxial and fairly well matched to the silicon lattice. However, there is a twist, producing a rotational strain (Bond length may be slightly changed, however, it is a minor effect). The newly arrived silicon layer shares this rotational strain until enough silicon has been deposited. By then, most of the strain is pushed out of the silicon and concentrated in the SiOx layer in much the same way as the usual strain-layer epitaxy.
Further, the invention includes a method of introducing other elements such as is N, C, P, S, Sb, As, H, etc., which serve to replace oxygen for forming a barrier structure with silicon. Inclusion of different elements in place of or in addition to oxygen may also serve as a diffusion barrier in gettering, or trapping, other elements. In this regard, the Si/O superlattice and EpiSiOx may be reinforced by further diffusion of oxygen through the Si capping layer to be trapped by the barrier layers (Nakashima). The benefit is obvious: (a) the cap layer is epitaxial and defect free, serving as an ideal medium for FET devices, and (b) the epitaxial layer may be made thin enough itself to form barriers for quantum wells and for quantum devices such as the RTD, and quantum transistor and the single electron transistor.
This invention further provides a method to adjust (change) the dielectric constant and barrier height of the barrier layers, both Si/O and EpiSiOx, by controlling the oxygen (or substitute element) content of the barrier. This can be accomplished by adjusting the level of oxygen during simultaneous deposition for EpiSiOx and controlling the percentage of monolayer oxygen coverage used in Si/O. In the EpiSiOx the oxygen can further be adjusted during deposition to produce a barrier with a controlled gradient of oxygen content across the barrier thickness. In Si/O this can be accomplished by repeating layers with varying oxygen exposure per layer. As we discussed before that the thicker the layer of epitaxially grown SiOx, the thicker is the subsequent Si growth for full recovery of epitaxy. Therefore, for thicker barrier requirements, we need to repeat the process, to build up the thickness of the barrier for a given application.
Both Si/O and EpiSiOx can be fabricated using Molecular Beam Epitaxy (MBE), and in some cases with Chemical Vapor Deposition (CVD) or by any other means known to those familiar with the state of the art.
Any of the above combinations of Si/O and/or EpiSiOx, either individually or in multiple layers, will from hereon be referred to as said barrier.
This invention further provides a Silicon-on-Insulator (SOI) structure where said barrier is used as the insulator in the SOI with an epitaxial silicon device layer adjacent to this layer. This barrier layer can be used as is or can be enhanced by a high temperature oxidation procedure as described by Nakashima et al (21).
The invention provides for quantum devices where said barrier is used as a barrier with silicon to produce Resonant Tunneling Devices (RTD), (Silicon RTD has been experimentally realized by researchers in Inst. Of Semiconductor Physics, Kiev, Ukraine: Preliminary in Litovcheko et al., JVST, B15, 439 (1997)(8)), quantum well devices, single electron field effect transistors (SEFET), etc. It also provides a metal-oxide-semi-conductor field-effect transistor (MOSFET) where the gate xe2x80x9coxidexe2x80x9d is replaced completely or partially by said barrier. Additionally, this just described MOSFET can have a layer of said barrier just below the channel region of the device to produce a true two-dimensional electron gas between the source and drain thereby enhancing the mobility and performance of the device.
The main advantage of the present invention is that the said barrier allows for the continued epitaxial growth of silicon adjacent to this layer which is substantially defect free. This can be repeated to produce a stack of alternating said barrier and epitaxial device grade silicon in order to form a 3-dimensional structure for producing the 3-dimensional integrated circuits (3D-IC) of the future in silicon (see FIG. 7). This invention makes it possible to form the active channel, the contacts, and the insulating regions epitaxially. For example, the channel is made with epitaxial silicon on top of the EpiSiOx with the source and drain by conventional doping. The conventional n+ or p+ doping on top of an insulating layer serves as a gate (there is no need for polysilicon gate contact because the whole structure preserves epitaxy!) This 3D possibility using EpiSiOx propels the electronic industry into the 21st century!
An important aspect of the present invention is the possibility of building a 3D-IC of the future in silicon because all the components can now be built out of this epitaxial system forming barriers, channels, electrical insulation, etc. Such a 3D-IC can circumvent many problems of interconnection, heat dissipation and others. In the immediate future, a high speed, high efficiency, all silicon FET can be better designed with the EpiSiOx.